1. Field
This disclosure relates generally to a multiplexer and, more specifically, to a transmission gate multiplexer.
2. Related Art
As is known, a transmission gate typically includes a parallel combination of an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and a p-channel MOSFET. An input at a gate of one of the MOSFETs is complementary to an input at a gate of the remaining MOSFET. That is, when an input to a gate of the n-channel MOSFET is a digital zero ‘0’, an input to a gate of the p-channel MOSFET is a digital one ‘1’. In this case, both of the MOSFETs are turned off and an input of the transmission gate is not connected to an output of the transmission gate. Similarly, when the gate input to the n-channel MOSFET is a digital one ‘1’, the gate input to the p-channel MOSFET is a digital zero ‘0’. In this case, both of the MOSFETs are turned on and an input signal at an input of the transmission gate is passed by the transmission gate to an output of the transmission gate. In general, the utilization of a transmission gate essentially eliminates undesirable threshold voltage effects that may result in loss of logic levels (irrespective of a logic level, i.e., one ‘1’ or zero ‘0’, of an input signal).
As is also known, a multiplexer is an electronic device that includes multiple inputs and a single output. A multiplexer selects a single one of multiple data sources, which are each coupled to respective inputs of the multiplexer, and provides the selected data source on a single output of the multiplexer. In high-speed circuit design applications, multiplexers have typically utilized transmission gates. In general, conventional multiplexers that have employed transmission gates have exhibited decreased latency, as compared to conventional multiplexers that have implemented NAND-NAND or AND-OR-Invert (AOI) gate structures. However, in conventional multiplexers that have employed transmission gates, as the number of multiplexer inputs has increased, a diffusion capacitance at a common output node of the transmission gates has also increased. When the diffusion capacitance reaches a threshold level, a signal speed at the common output node of the multiplexer has decreased to a point that cancels an increase provided by utilizing transmission gates. Unfortunately, in order to reduce logic stages, reduce latency, and to minimize macro or chip area, it is often desirable to create wide multiplexers. Another downside to increasing a width of a multiplexer is that a select circuit load is also increased. Moreover, as noted above, in multiplexers that employ transmission gates, increasing a width of the multiplexer has caused a common output node of the transmission gates to become more heavily loaded, as additional transmission gates are added to the multiplexer (i.e., as the number of multiplexer inputs is increased).
With reference to FIG. 1, a relevant portion of a conventional 8:1 multiplexer 100 is depicted that includes eight select signals (i.e., sel0 through sel7) that are employed to select one data signal (i.e., one of data signals din0 through din7). The conventional multiplexer 100 includes eight transmission gates 104 whose outputs are coupled to a common output node 106, which is coupled to an input of an inverter 108. Due to the number of the transmissions gates 104 coupled to the common output node 106, the multiplexer 100 may exhibit a relatively large diffusion capacitance, as well as a relatively large leakage current. Turning to FIG. 2, a select circuit 200 is depicted that provides the select signals for the multiplexer 100. The select circuit 200 receives a three-bit binary coded select signal (including bits b0, b1, and b2) that is decoded to provide an appropriate one of the select signals (i.e., sel0 through sel7). As is shown, the select circuit 200 employs two inverters 202 for each of the three-bit binary coded select signals. Signals provided by the inverters 202 are provided to appropriate inputs of three-input NAND gates 204, whose outputs are provided to respective inverters 206.